Network Processors: Memory - Processor Tradeoffs

MARK FRANKLIN
  Urbauer Professor
  of Electrical Engineering & Computer Science
  Washington University
  St. Louis

ABSTRACT:

  To adapt to new protocols, services, standards and network
  applications, many modern routers are equipped with general purpose
  processing capabilities (i.e., NETWORK PROCESSORS) to handle packet
  traffic primarily in software rather than in dedicated hardware.  This
  talk is aimed at examining certain tradeoffs associated with the
  design of a selected style of single chip network processor.  To keep
  up with increasing line speeds, network processors often contain a
  group of parallel processors, each with its own cache memory. 
  Performance can be improved by increasing the number of processors per
  network processor chip (increasing overall processing capabilities),
  or by increasing the cache size associated with each processor
  (decreasing memory access faults).  Chip area constraints however
  result in the presence of a tradeoff between number of processors and
  the size of cache memory.  This tradeoff and selection of the optimal
  design point is considered using a combination of analytic models and
  benchmarking results.  A benchmark, COMMBENCH, which has been designed
  to reflect the type of load encounter by a network processor will be
  presented.  If time permits, an interesting issue associated with
  scheduling packets on such processors will also be discussed.